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    Design Recipes for FPGAs: Using Verilog and VHDL

    Design Recipes for FPGAs by Wilson, Peter;

    Using Verilog and VHDL

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      • Publisher's listprice EUR 49.00
      • The price is estimated because at the time of ordering we do not know what conversion rates will apply to HUF / product currency when the book arrives. In case HUF is weaker, the price increases slightly, in case HUF is stronger, the price goes lower slightly.

        19 139 Ft (18 228 Ft + 5% VAT)
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    Product details:

    • Edition number 2
    • Publisher Elsevier Science
    • Date of Publication 23 September 2015

    • ISBN 9780080971292
    • Binding Paperback
    • No. of pages392 pages
    • Size 234x190 mm
    • Weight 790 g
    • Language English
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    Long description:

    Design Recipes for FPGAs provides a rich toolbox of design techniques and templates to solve practical, every-day problems using FPGAs. Using a modular structure, it provides design techniques and templates at all levels, together with functional code, which you can easily match and apply to your application. Written in an informal and easy to grasp style, this invaluable resource goes beyond the principles of FPGAs and hardware description languages to demonstrate how specific designs can be synthesized, simulated and downloaded onto an FPGA. In addition, the book provides advanced techniques to create 'real world' designs that fit the device required and which are fast and reliable to implement.

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    Table of Contents:

    Part 1: Overview
    1: Introduction
    2: An FPGA Primer
    3: A VHDL Primer: The Essentials
    4: A Verilog Primer: The Essentials
    5: Design Automation of FPGAs
    6: Synthesis

    Part 2: Introduction to FPGA Applications
    7: High Speed Video Application
    8: Simple Embedded Processors

    Part 3: Designer's Toolbox
    9: Digital Filters
    10: Secure Systems
    11: Memory
    12: PS/2 Mouse Interface
    13: PS/2 Keyboard Interface
    14: A Simple VGA Interface
    15: Serial Communications

    Part 4: Optimizing Designs
    16: Design Optimization
    17: Behavioral Modeling in using HDLs
    18: Mixed Signal Modeling
    19: Design Optimization Example: DES

    Part 5: Fundamental Techniques
    20: Latches, Flip-Flops, and Registers
    21: ALU Functions
    22: Finite State Machines in VHDL and Verilog
    23: Fixed Point Arithmetic
    24: Counters
    25: Decoders and Multiplexers
    26: Multiplication-
    27: Simple 7-Segment (LCD) Displays

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