Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006, Proceedings
Series: Lecture Notes in Computer Science; 4148;
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Product details:
- Edition number 2006
- Publisher Springer
- Date of Publication 8 September 2006
- Number of Volumes 1 pieces, Book
- ISBN 9783540390947
- Binding Paperback
- No. of pages677 pages
- Size 235x155 mm
- Weight 1056 g
- Language English
- Illustrations XVI, 677 p. 0
Categories
Short description:
This book constitutes the refereed proceedings of the 16th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2006. The book presents 41 revised full papers and 23 revised poster papers together with 4 key notes and 3 industrial abstracts. Topical sections include high-level design, power estimation and modeling memory and register files, low-power digital circuits, busses and interconnects, low-power techniques, applications and SoC design, modeling, and more.
MoreLong description:
Welcome to the proceedings of PATMOS 2006, the 16th in a series of international workshops. PATMOS 2006 was organized by LIRMM with CAS technical - sponsorship and CEDA sponsorship. Over the years, the PATMOS workshop has evolved into an important European event, where researchers from both industry and academia discuss and investigate the emerging challenges in future and contemporary applications, design methodologies, and tools required for the development of upcoming generations of integrated circuits and systems. The technical program of PATMOS 2006 contained state-of-the-art technical contributions, three invited talks, a special session on hearing-aid design, and an embedded tutorial. The technical program focused on timing, performance and power consumption, as well as architectural aspects with particular emphasis on modeling, design, characterization, analysis and optimization in the nanometer era. The Technical Program Committee, with the assistance of additional expert reviewers, selected the 64 papers presented at PATMOS. The papers were organized into 11 technical sessions and 3 poster sessions. As is always the case with the PATMOS workshops, full papers were required, and several reviews were received per manuscript.
MoreTable of Contents:
Session 1 ? High-Level Design.- Session 2 ? Power Estimation / Modeling.- Session 3 ? Memory and Register Files.- Session 4 ? Low-Power Digital Circuits.- Session 5 ? Busses and Interconnects.- Session 6 ? Low Power Techniques.- Session 7 ? Applications and SoC Design.- Session 8 ? Modeling.- Session 9 ? Digital Circuits.- Session 10 ? Reconfigurable and Programmable Devices.- Poster 1.- Poster 2.- Poster 3.- Keynotes.- Industrial Session.
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