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  • Electronic Design Automation: Synthesis, Verification, and Test

    Electronic Design Automation by Wang, Laung-Terng; Chang, Yao-Wen; Cheng, Kwang-Ting (Tim);

    Synthesis, Verification, and Test

    Series: Systems on Silicon;

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      • Publisher's listprice EUR 96.95
      • The price is estimated because at the time of ordering we do not know what conversion rates will apply to HUF / product currency when the book arrives. In case HUF is weaker, the price increases slightly, in case HUF is stronger, the price goes lower slightly.

        40 210 Ft (38 295 Ft + 5% VAT)
      • Discount 10% (cc. 4 021 Ft off)
      • Discounted price 36 189 Ft (34 466 Ft + 5% VAT)

    40 210 Ft

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    printed on demand

    Why don't you give exact delivery time?

    Delivery time is estimated on our previous experiences. We give estimations only, because we order from outside Hungary, and the delivery time mainly depends on how quickly the publisher supplies the book. Faster or slower deliveries both happen, but we do our best to supply as quickly as possible.

    Product details:

    • Publisher Elsevier Science
    • Date of Publication 26 March 2009

    • ISBN 9780123743640
    • Binding Hardback
    • No. of pages972 pages
    • Size 234x190 mm
    • Weight 1760 g
    • Language English
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    Long description:

    "This book provides broad and comprehensive coverage of the entire EDA flow. EDA/VLSI practitioners and researchers in need of fluency in an ""adjacent"" field will find this an invaluable reference to the basic EDA concepts, principles, data structures, algorithms, and architectures for the design, verification, and test of VLSI circuits. Anyone who needs to learn the concepts, principles, data structures, algorithms, and architectures of the EDA flow will benefit from this book."

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    Table of Contents:

    Chapter 1: Introduction
    Chapter 2: Fundamentals of CMOS Design
    Chapter 3: Design for Testability
    Chapter 4: Fundamentals of Algorithms
    Chapter 5: Electronic System-Level Design and High-Level Synthesis
    Chapter 6: Logic Synthesis in a Nutshell
    Chapter 7: Test Synthesis
    Chapter 8: Logic and Circuit Simulation
    Chapter 9:ï¿1⁄2Functional Verification
    Chapter 10: Floorplanning
    Chapter 11: Placement
    Chapter 12: Global and Detailed Routing
    Chapter 13: Synthesis of Clock and Power/Ground Networks
    Chapter 14: Fault Simulation and Test Generation.

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