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Product details:
- Edition number 2
- Publisher Morgan Kaufmann
- Date of Publication 1 July 2008
- ISBN 9781558608658
- Binding Paperback
- No. of pages528 pages
- Size 234x190 mm
- Weight 890 g
- Language English
- Illustrations Illustrated 0
Categories
Short description:
A guide to VHDL for digital system modeling. It aims to show how VHDL modeling fits into a design flow, starting from high-level design and proceeding through detailed design and verification, synthesis, FPGA place and route, and final timing verification.
MoreLong description:
The Student's Guide to VHDL is a condensed edition of The Designer's Guide to VHDL, the most widely used textbook on VHDL for digital system modeling. The Student's Guide is targeted as a supplemental reference book for computer organization and digital design courses.Since publication of the first edition of The Student's Guide, the IEEE VHDL and related standards have been revised. The Designer's Guide has been revised to reflect the changes, so it is appropriate that The Student's Guide also be revised. In The Student's Guide to VHDL, 2nd Edition, we have included a design case study illustrating an FPGA-based design flow. The aim is to show how VHDL modeling fits into a design flow, starting from high-level design and proceeding through detailed design and verification, synthesis, FPGA place and route, and final timing verification. Inclusion of the case study helps to better serve the educational market. Currently, most college courses do not formally address the details of design flow. Students may be given informal guidance on how to proceed with lab projects. In many cases, it is left to students to work it out for themselves. The case study in The Student's Guide provides a reference design flow that can be adapted to a variety of lab projects.
MoreTable of Contents:
Preface1 Fundamental Concepts2 Scalar Data Types and Operations3 Sequential Statements4 Composite Data Types and Operations5 Basic Modeling Constructs6 Subprograms7 Packages and Use Clauses8 Aliases9 Resolved Signals10 Generics11 Components12 Generate Statements13 Design for Synthesis14 Case Study: System Design using the Gumnut CoreA Standard PackagesB VHDL SyntaxC Differences Among VHDL VersionsD Answers to ExercisesReferencesIndex
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