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  • RISC-V System-on-Chip Design

    RISC-V System-on-Chip Design by Harris, David; Stine, James; Harris, Sarah; Thompson, Rose;

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      • Publisher's listprice EUR 86.95
      • The price is estimated because at the time of ordering we do not know what conversion rates will apply to HUF / product currency when the book arrives. In case HUF is weaker, the price increases slightly, in case HUF is stronger, the price goes lower slightly.

        36 062 Ft (34 345 Ft + 5% VAT)
      • Discount 10% (cc. 3 606 Ft off)
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    36 062 Ft

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    Product details:

    • Publisher Elsevier Science
    • Date of Publication 15 May 2026

    • ISBN 9780323994989
    • Binding Paperback
    • No. of pages600 pages
    • Size 235x191 mm
    • Weight 450 g
    • Language English
    • 700

    Categories

    Long description:

    RISC-V Microprocessor System-On-Chip Design is written to be accessible to an advanced undergraduate audience with limited background. It explains concepts from operating systems, VLSI, and memory systems as necessary, and High school mathematics is sufficient preparation for most of the book, although the floating point and division chapters will be primarily of interest to those with a curiosity about computer arithmetic. Like Harris and Harris’s Digital Design and Computer Architecture textbooks, this book will appeal to students with easy-to-read and complete explanations, sidebars, and occasional humor and cartoons.

    It comes with an open-source implementation and will include end-of-chapter problems to extend the RISC-V processor in various ways. Ancillary materials include a GitHub repository with complete open-source SystemVerilog code, validation code in C and assembly language, and code for benchmarking and booting Linux.

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    Table of Contents:

    Preface
    How to Use This Book
    Acknowledgements
    About the Authors
    Foreword

    01. A Brief History of Computer Design
    02. Introduction to RISC-V
    03. RISC-V Software Tool Flow
    04. HDL Design Practices
    05. Design Verification
    06. Logic Synthesis
    07. Pipelined Core
    08. Privileged Operations
    09. Bus Interface
    10. Caches
    11. Memory Management Unit
    12. Load/Store Unit
    13. Instruction Fetch Unit
    14. Extensions: C (Compressed)
    15. Extensions: M (Multiply and Divide)
    16. Extensions: F/D/Q/Zfh/Zfa (Floating-Point)
    17. Extensions: A (Atomic)
    18. Extensions: Zb* and Zk* (Bit Manipulation and Cryptography)
    19. Other Extensions
    20. Peripherals
    21. Benchmarking
    22. Linux
    23. FPGA Implementation
    Appendix A Wally Synopsis
    Appendix B Hitchhiker’s Guide to Linux
    Appendix C Version Control using Git
    Appendix D Tcl Book of Armaments
    Appendix E Floating-Point Implementation
    Bibliography
    Index

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