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    RISC-V System-On-Chip Design

    RISC-V System-On-Chip Design by Harris, David; Stine, James; Harris, Sarah;

      • GET 10% OFF

      • The discount is only available for 'Alert of Favourite Topics' newsletter recipients.
      • Publisher's listprice EUR 86.95
      • The price is estimated because at the time of ordering we do not know what conversion rates will apply to HUF / product currency when the book arrives. In case HUF is weaker, the price increases slightly, in case HUF is stronger, the price goes lower slightly.

        36 884 Ft (35 127 Ft + 5% VAT)
      • Discount 10% (cc. 3 688 Ft off)
      • Discounted price 33 195 Ft (31 614 Ft + 5% VAT)

    36 884 Ft

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    Why don't you give exact delivery time?

    Delivery time is estimated on our previous experiences. We give estimations only, because we order from outside Hungary, and the delivery time mainly depends on how quickly the publisher supplies the book. Faster or slower deliveries both happen, but we do our best to supply as quickly as possible.

    Long description:

    RISC-V Microprocessor System-On-Chip Design is written to be accessible to an advanced undergraduate audience with limited background. It explains concepts from operating systems, VLSI, and memory systems as necessary, and High school mathematics is sufficient preparation for most of the book, although the floating point and division chapters will be primarily of interest to those with a curiosity about computer arithmetic. Like Harris and Harris’s Digital Design and Computer Architecture textbooks, this book will appeal to students with easy-to-read and complete explanations, sidebars, and occasional humor and cartoons.

    It comes with an open-source implementation and will include end-of-chapter problems to extend the RISC-V processor in various ways. Ancillary materials include a GitHub repository with complete open-source SystemVerilog code, validation code in C and assembly language, and code for benchmarking and booting Linux.

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    Table of Contents:

    1. Introduction

    Part 1: RISC-V Architecture
    2. RISC-V Architecture
    3. Assembly Language Programming
    4. C Programming

    Part 2: RISC-V Microarchitecture
    5. Microarchitecture Overview
    6. Survey of Microarchitectures
    7. RISC-V Pipelined Microarchitecture
    8. Privileged Operations
    9. AHB Interface
    10. Virtual Memory
    11. Branch Prediction
    12. RISC-V Superscalar Microarchitecture
    13. RISC-V Threaded Microarchitecture
    14. Extensions: Compressed Instructions
    15. Extensions: Multiplication and Division
    16. Extensions: Floating Point
    17. Extensions: Atomic Operations
    18. More Bus Interfaces
    19. Peripherals
    20. Multicore
    21. SIMD
    22. Vector
    23. Bit Manipulation
    24. Crypto

    Part 3: Validation
    25. Logic Verification
    26. Performance Validation: Benchmarking
    27. Linux Boot

    Part 4: Implementation
    28. FPGA Implementation
    29. CMOS for Microarchitects
    30. CMOS Implementation
    31. Silicon Debug

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    RISC-V System-On-Chip Design

    RISC-V System-On-Chip Design

    Harris, David; Stine, James; Harris, Sarah;

    36 884 HUF

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