RISC-V System-On-Chip Design
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Product details:
- Publisher Morgan Kaufmann
- Date of Publication 14 November 2025
- ISBN 9780323994989
- Binding Paperback
- No. of pages600 pages
- Size 235x191 mm
- Weight 450 g
- Language English 700
Categories
Long description:
RISC-V Microprocessor System-On-Chip Design is written to be accessible to an advanced undergraduate audience with limited background. It explains concepts from operating systems, VLSI, and memory systems as necessary, and High school mathematics is sufficient preparation for most of the book, although the floating point and division chapters will be primarily of interest to those with a curiosity about computer arithmetic. Like Harris and Harris’s Digital Design and Computer Architecture textbooks, this book will appeal to students with easy-to-read and complete explanations, sidebars, and occasional humor and cartoons.
It comes with an open-source implementation and will include end-of-chapter problems to extend the RISC-V processor in various ways. Ancillary materials include a GitHub repository with complete open-source SystemVerilog code, validation code in C and assembly language, and code for benchmarking and booting Linux.
- Covers detailed design for all components of a nontrivial microprocessor
- Provides detailed explanations on the implementation of RISC-V microprocessors
- Uses open-source SystemVerilog code and test cases for the entire processor, including single-issue and superscalar cores, multicore, all extensions (including multiplication/division, floating point, and atomic memory operations), and common peripherals
- Enables users to build scripts to implement the processor on the open-source Skywater process
Table of Contents:
1. Introduction
Part 1: RISC-V Architecture
2. RISC-V Architecture
3. Assembly Language Programming
4. C Programming
Part 2: RISC-V Microarchitecture
5. Microarchitecture Overview
6. Survey of Microarchitectures
7. RISC-V Pipelined Microarchitecture
8. Privileged Operations
9. AHB Interface
10. Virtual Memory
11. Branch Prediction
12. RISC-V Superscalar Microarchitecture
13. RISC-V Threaded Microarchitecture
14. Extensions: Compressed Instructions
15. Extensions: Multiplication and Division
16. Extensions: Floating Point
17. Extensions: Atomic Operations
18. More Bus Interfaces
19. Peripherals
20. Multicore
21. SIMD
22. Vector
23. Bit Manipulation
24. Crypto
Part 3: Validation
25. Logic Verification
26. Performance Validation: Benchmarking
27. Linux Boot
Part 4: Implementation
28. FPGA Implementation
29. CMOS for Microarchitects
30. CMOS Implementation
31. Silicon Debug
