Computer Architecture
A Quantitative Approach
Series: The Morgan Kaufmann Series in Computer Architecture and Design;
- Publisher's listprice EUR 94.95
-
39 380 Ft (37 505 Ft + 5% VAT)
The price is estimated because at the time of ordering we do not know what conversion rates will apply to HUF / product currency when the book arrives. In case HUF is weaker, the price increases slightly, in case HUF is stronger, the price goes lower slightly.
- Discount 10% (cc. 3 938 Ft off)
- Discounted price 35 442 Ft (33 755 Ft + 5% VAT)
Subcribe now and take benefit of a favourable price.
Subscribe
39 380 Ft
Availability
Not yet published.
Why don't you give exact delivery time?
Delivery time is estimated on our previous experiences. We give estimations only, because we order from outside Hungary, and the delivery time mainly depends on how quickly the publisher supplies the book. Faster or slower deliveries both happen, but we do our best to supply as quickly as possible.
Product details:
- Edition number 7
- Publisher Elsevier Science
- Date of Publication 17 November 2025
- ISBN 9780443154065
- Binding Paperback
- No. of pages936 pages
- Size 235x191 mm
- Weight 450 g
- Language English 700
Categories
Long description:
Computer Architecture: A Quantitative Approach, has been considered essential reading by instructors, students and practitioners of computer design for nearly 30 years. The seventh edition of this classic textbook from John Hennessy and David Patterson, winners of the 2017 ACM A.M. Turing Award recognizing contributions of lasting and major technical importance to the computing field, along with new author Christos Kozyrakis, is fully revised with the latest developments in processor and system architecture.
True to its original mission of demystifying computer architecture, this edition continues the longstanding tradition of focusing on areas where the most exciting computing innovation is happening, while always keeping an emphasis on good engineering design.
Table of Contents:
Printed Text
1. Fundamentals of Quantitative Design and Analysis
2. Memory Hierarchy Design
3. Instruction-Level Parallelism and Its Exploitation
4. Data-Level Parallelism in Vector, SIMD, and GPU Architectures
5. Thread-Level Parallelism
6. Warehouse-Scale Systems for Utility Computing
7. Domain Specific Architectures
A. Instruction Set Principles
B. Review of Memory Hierarchy
C. Pipelining: Basic and Intermediate Concepts
Online
D. Storage Systems
E. Embedded Systems
F. Interconnection Networks
G. Vector Processors
H. Hardware and Software for VLIW and EPIC
I. Large-Scale Multiprocessors and Scientific Applications
J. Computer Arithmetic
K. Survey of Instruction Set Architectures
L. Advanced Concepts on Address Translation
M. Historical Perspectives and References
