• Contact

  • Newsletter

  • About us

  • Delivery options

  • Prospero Book Market Podcast

  • News

  • Comprehensive Functional Verification: The Complete Industry Cycle

    Comprehensive Functional Verification by Wile, Bruce; Goss, John; Roesner, Wolfgang;

    The Complete Industry Cycle

    Series: Systems on Silicon;

      • GET 20% OFF

      • The discount is only available for 'Alert of Favourite Topics' newsletter recipients.
      • Publisher's listprice EUR 72.95
      • The price is estimated because at the time of ordering we do not know what conversion rates will apply to HUF / product currency when the book arrives. In case HUF is weaker, the price increases slightly, in case HUF is stronger, the price goes lower slightly.

        30 945 Ft (29 471 Ft + 5% VAT)
      • Discount 20% (cc. 6 189 Ft off)
      • Discounted price 24 756 Ft (23 577 Ft + 5% VAT)

    30 945 Ft

    db

    Availability

    printed on demand

    Why don't you give exact delivery time?

    Delivery time is estimated on our previous experiences. We give estimations only, because we order from outside Hungary, and the delivery time mainly depends on how quickly the publisher supplies the book. Faster or slower deliveries both happen, but we do our best to supply as quickly as possible.

    Product details:

    • Publisher Morgan Kaufmann
    • Date of Publication 29 June 2005

    • ISBN 9780127518039
    • Binding Hardback
    • No. of pages704 pages
    • Size 234x190 mm
    • Weight 1540 g
    • Language English
    • 0

    Categories

    Long description:

    One of the biggest challenges in chip and system design is determining whether the hardware works correctly. That is the job of functional verification engineers and they are the audience for this comprehensive text from three top industry professionals.As designs increase in complexity, so has the value of verification engineers within the hardware design team. In fact, the need for skilled verification engineers has grown dramatically--functional verification now consumes between 40 and 70% of a project's labor, and about half its cost. Currently there are very few books on verification for engineers, and none that cover the subject as comprehensively as this text. A key strength of this book is that it describes the entire verification cycle and details each stage. The organization of the book follows the cycle, demonstrating how functional verification engages all aspects of the overall design effort and how individual cycle stages relate to the larger design process. Throughout the text, the authors leverage their 35 plus years experience in functional verification, providing examples and case studies, and focusing on the skills, methods, and tools needed to complete each verification task.

    More

    Table of Contents:


    Part I: Introduction to Verification

    Chapter 1: Verification in the Chip Design Process
    Chapter 2: Verification Flow
    Chapter 3: Fundamentals of Simulation Based Verification
    Chapter 4: The Verification Plan

    Part II: Simulation-Based Verification

    Chapter 5: HDLs and Simulation Engines
    Chapter 6: Creating Environments
    Chapter 7: Strategies for Simulation-based Stimulus Generation
    Chapter 8: Strategies for Results Checking in Chapter 9: Pervasive Function Verification
    Chapter 10: Re-Use Strategies and System Simulation

    Part III: Formal Verification

    Chapter 11 Introduction to Formal Verification
    Chapter 12 Using Formal Verification

    Part IV: Comprehensive Verification

    Chapter 13: Completing the Verification Cycle
    Chapter 14: Advanced Verification Techniques

    Part V: Case Studies

    Chapter 15: Case Studies

    Glossary
    References

    More